On the implementation of bus-based architectures for LDPC decoding

Three families of architectures for LDPC decoding are presented in this paper, aiming at the reduction of the interconnection complexity dominant in an LDPC decoder. The proposed architectures explore tradeoffs between the interconnection complexity, delay, and decoding performance. A graph-based technique is introduced that allows the formation of groups of calculations, such that inter-group communication is minimized. The formed groups are subsequently mapped onto processor units. Furthermore, a technique to achieve full utilization of processors under a constraint on the number of busses is discussed and a corresponding architecture, as well as a hybrid of the multi-bus and grouped-calculations architecture.