Title :
Merged DRAM-logic in the year 2001
Author :
Diodato, P.W. ; Noda, K. ; Wong, Y.-H. ; Drynan, J.M. ; Liu, C.T. ; Lee, K.H. ; Dail, R. ; Lindenberger, W.S. ; Dumbri, A.C. ; Depaolis, M.V. ; Clemens, J.T. ; Troutman, W.W. ; Nakamae, M.
Author_Institution :
Lucent Technol., Murray Hill, NJ, USA
Abstract :
The desire to enhance memory bandwidth in high performance computing components is overwhelming, and early attempts to combine large memories with high performance logic in a single silicon integrated circuit are numerous. However, existing implementations of a combined (merged) memory-logic technology are unsatisfactory (because of high cost) and complicated (because the technologies used for high-performance logic and high-density memory are disparate). The research reported here will explain the joint technology development of two corporations working on a merged memory-logic technology in terms of: (1) memory cell design comparisons, (2) transistor and capacitor specifications, (3) process technology tradeoffs, and (4) circuit simulations
Keywords :
DRAM chips; cellular arrays; circuit simulation; integrated circuit design; memory architecture; capacitor specifications; circuit simulations; high performance computing components; high-density memory; memory bandwidth; memory cell design comparisons; merged DRAM-logic; process technology tradeoffs; Bandwidth; Circuit simulation; Cost function; Logic arrays; Logic circuits; National electric code; Random access memory; Silicides; System performance; Threshold voltage;
Conference_Titel :
Memory Technology, Design and Testing, 1998. Proceedings. International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-8494-1
DOI :
10.1109/MTDT.1998.705942
