DocumentCode
2003173
Title
BIST for word-oriented DRAM
Author
Zakrevski, L. ; Karpovsky, M. ; Yang, S.H.
Author_Institution
Dept. of Comput. Eng., Boston Univ., MA, USA
fYear
1998
fDate
24-25 Aug 1998
Firstpage
31
Lastpage
37
Abstract
The problem of exhaustive test generation for detection of coupling faults between cells in word-oriented memories is considered. According to this fault model, contents of any w-bit memory word in a memory with n words, or ability to change this content, is influenced by the contents of any other s-l words in the memory. A near optimal iterative method for construction of test patterns is proposed. The systematic structure of the proposed test results in simple BIST implementations
Keywords
DRAM chips; built-in self test; cellular arrays; fault diagnosis; integrated circuit testing; iterative methods; cell coupling faults; exhaustive test generation; fault model; near optimal iterative method; test patterns; word-oriented DRAM; Automatic testing; Built-in self-test; Costs; Electrical capacitance tomography; Fault detection; Random access memory; Reliability engineering; SRAM chips; System testing; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Technology, Design and Testing, 1998. Proceedings. International Workshop on
Conference_Location
San Jose, CA
Print_ISBN
0-8186-8494-1
Type
conf
DOI
10.1109/MTDT.1998.705943
Filename
705943
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