Title :
Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuation
Author :
Takeuchi, K. ; Tatsumi, T. ; Furukawa, A.
Author_Institution :
Silicon Syst. Res. Labs., NEC Corp., Sagamihara, Japan
Abstract :
A simple model is proposed, which is able to calculate V/sub TH/ standard deviation due to random dopant placement in the channel, for arbitrary vertical impurity distributions. Substantial decrease in V/sub TH/ fluctuation, while keeping V/sub TH/ the same, is confirmed for low surface impurity channel MOSFETs, in agreement with the model prediction.
Keywords :
MOSFET; doping profiles; semiconductor device models; semiconductor doping; channel engineering; model; random dopant placement; standard deviation; surface impurity channel MOSFET; threshold voltage fluctuation; vertical impurity distribution; Doping profiles; Fluctuations; Impurities; MOSFETs; National electric code; Power system modeling; Predictive models; Semiconductor process modeling; Silicon; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-4100-7
DOI :
10.1109/IEDM.1997.650512
