DocumentCode :
2003738
Title :
Adaptive genetic algorithm based approach for evolutionary design and multi-objective optimization of logic circuits
Author :
Zhao, Shuguang ; Zhao, Jianxun ; Jiao, Licheng
Author_Institution :
Sch. of Electron. Eng., Xidian Univ., Xi´´an, China
fYear :
2005
fDate :
29 June-1 July 2005
Firstpage :
67
Lastpage :
72
Abstract :
Evolvable hardware is an artificial-evolution based promising path to automated design of circuits and discovery of fancy modules and principles. To improve gate-level evolution of logic circuits in speed and scale for synthetically optimized design results, an adaptive genetic algorithm based approach is presented in this paper. First, it employs an array-model-based encoding scheme that allows flexible changes of comprised logic cells´ logic functions and interconnections. Second, it adopts a multi-objective fitness evaluation mechanism with weight-vector adapting and circuit simulation. Third, it features an adaptation strategy that enables crossover probability and mutation probability to vary with the individual diversity and the genetic process. By virtue of these measures, it was validated effective, efficient and innovative by some experiments on arithmetic circuits, in which we obtained functionally correct circuits with novel structures, fewer logic cells and higher operating speed as compared with results of some conventional or evolutionary approaches.
Keywords :
circuit optimisation; circuit simulation; genetic algorithms; logic arrays; logic circuits; logic design; adaptive genetic algorithm; arithmetic circuit; array model based encoding; artificial evolution; circuit automated design; circuit simulation; crossover probability; evolutionary design; evolvable hardware; fitness evaluation; gate level evolution; interconnection; logic circuit; logic function; multiobjective optimization; mutation probability; weightvector adapting; Algorithm design and analysis; Circuit simulation; Design optimization; Encoding; Genetic algorithms; Hardware; Integrated circuit interconnections; Logic arrays; Logic circuits; Logic functions;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Evolvable Hardware, 2005. Proceedings. 2005 NASA/DoD Conference on
ISSN :
1550-6029
Print_ISBN :
0-7695-2399-4
Type :
conf
DOI :
10.1109/EH.2005.7
Filename :
1508483
Link To Document :
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