Title :
A fully planarized 6-level-metal CMOS technology for 0.25-0.18 micron foundry manufacturing
Author :
Lin, T. ; Chen, C. ; Hsu, S.Y. ; Tsai, M.J. ; Yew, T.R. ; Chou, J.W. ; Haung, K.T. ; Wu, J.Y. ; Ku, Y.C. ; Liu, C.C. ; Yang, M.S. ; Yeh, W.K. ; Huang, C.H. ; Lur, W. ; Huang, H.S. ; Sun, S.W.
Author_Institution :
Technol. Dev. Div., United Microelectron. Corp., Hsin-Chu, Taiwan
Abstract :
A 0.25 /spl mu/m CMOS technology, with 6 layers of fully planarized interconnect, has been developed for versatile, flexible, and fast turn-around foundry manufacturing. A 0.6 /spl mu/m layout pitch has been successfully demonstrated for active, gate poly, and first metal layers. The 0.25 /spl mu/m, 50 A Tox and the 0.35 /spl mu/m, 65 A Tox devices were designed to support the 2.5 V core and the 3.3 V I/O circuits respectively on the same chip. In addition, high-performance 0.18 /spl mu/m, 40 A Tox transistors are also available for low-power applications at 1.8 V Vcc. Gate-delay is 40 p-sec at 2.5 V for the 0.25 /spl mu/m device, and 35 p-sec at 1.8 V for the 0.18 /spl mu/m device. The embedded 6 T SRAM cell size is 6.34 /spl mu/m/sup 2/. Considerations in process architecture and device design, relevant to foundry manufacturing, are also addressed on this 6-level-metal 0.25 /spl mu/m CMOS technology.
Keywords :
CMOS memory circuits; SRAM chips; integrated circuit interconnections; 0.25 to 0.18 micron; 1.8 to 2.5 V; 35 to 40 ps; 6-level-metal CMOS technology; device design; embedded 6 T SRAM cell; foundry manufacturing; fully planarized interconnect; gate delay; low-power Tox transistor; process architecture; CMOS technology; Circuits; Dielectrics; Foundries; Manufacturing processes; Planarization; Random access memory; Semiconductor device manufacture; Sun; Tungsten;
Conference_Titel :
Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-4100-7
DOI :
10.1109/IEDM.1997.650514
