• DocumentCode
    2004021
  • Title

    An EHW architecture for the design of unconstrained low-power FIR filters for sensor control using custom-reconfigurable technology

  • Author

    Stefatos, E.F. ; Arslan, T. ; Keymeulen, D. ; Ferguson, I.

  • Author_Institution
    Sch. of Eng. & Electron., Edinburgh Univ., UK
  • fYear
    2005
  • fDate
    June 29 2005-July 1 2005
  • Firstpage
    147
  • Lastpage
    153
  • Abstract
    This paper presents a power-optimized evolvable hardware (EHW) architecture that employs custom-reconfigurable technology. It comprises a preliminary research work towards the implementation of filtering circuits associated with the JPL-Boeing micro-machined gyroscope. Our scope is to implement a low-power, autonomously reconfigurable architecture that is tailored for the realization of arbitrary response FIR filters. For the purpose of this paper the hardware substrate comprises a reconfigurable 4/spl times/12 array, which consists of heterogeneous, configurable, arithmetic-logic units (CALUs). The implementation of the design is based on the primitive operator filter (POF) technique in order to evolve all the parts of a filter (unconstrained filter). Furthermore, a hybrid arithmetic approach is employed in order for the architecture to cope with overflow events. The paradigms of both lowpass and highpass filters are produced, using two different strategies of evolution. The obtained results demonstrate the physical characteristics of the reconfigurable substrate and the performance of the genetic algorithm (GA) in successfully designing FIR filters. Finally, the power results of the reconfigurable architecture (RA) are compared with these of the AT6000 series FPGAs and an algorithmically power-optimized, custom reprogrammable FIR core.
  • Keywords
    FIR filters; genetic algorithms; high-pass filters; logic arrays; logic design; low-pass filters; AT6000 series FPGA; JPL-Boeing micro-machined gyroscope; configurable arithmetic-logic units; custom-reconfigurable technology; filtering circuit; genetic algorithm; hardware substrate; highpass filter; hybrid arithmetic; low-power autonomous reconfigurable architecture; lowpass filter; power-optimized custom reprogrammable FIR core; power-optimized evolvable hardware architecture; primitive operator filter; reconfigurable array; reconfigurable substrate; sensor control; unconstrained low-power FIR filter; Algorithm design and analysis; Arithmetic; Circuits; Field programmable gate arrays; Filtering; Finite impulse response filter; Genetic algorithms; Gyroscopes; Hardware; Reconfigurable architectures;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Evolvable Hardware, 2005. Proceedings. 2005 NASA/DoD Conference on
  • Conference_Location
    Washington, DC, USA
  • ISSN
    1550-6029
  • Print_ISBN
    0-7695-2399-4
  • Type

    conf

  • DOI
    10.1109/EH.2005.8
  • Filename
    1508495