Low-frequency noise and DC characterization of ionization damage in a 1-μm SOI CMOS technology adapted for space applications

Author

Simoen, E. ; Magnusson, U. ; Van den Bosch, G. ; Smeys, P. ; Colinge, J.P. ; Claeys, C.

Author_Institution

IMEC, Leuven, Belgium

fYear

1993

fDate

13-16 Sep 1993

Firstpage

365

Lastpage

372

Abstract

The hardening of a standard 1-μm double layer metal CMOS SOI technology to a space environment is discussed. It is shown that a 50 krad(Si) hardened technology with VLSI performance can be obtained by changing a few steps in the basic process flow. Optimal results are obtained for a 850°C gate oxidation, combined with MESA-LOCOS isolation. Results of the radiation tests, using a ⁶⁰Co source, indicate changes in the threshold voltage of about 100 mV for a total dose of 100 krad(Si) and hole trapping factors in the range of 0.10-0.15. The increase in the low-frequency noise observed after irradiation is mainly related to the edge region of the MOS transistors

Keywords

CMOS integrated circuits; VLSI; gamma-ray effects; hole traps; radiation hardening (electronics); semiconductor device noise; semiconductor-insulator boundaries; silicon; 1 micron; 100 krad; 50 krad; 850 degC; DC characterization; MESA-LOCOS isolation; SOI CMOS technology; Si; VLSI performance; double layer metal; edge region; gate oxidation; hole trapping factors; ionization damage; low-frequency noise; process flow; radiation hardening; radiation tests; space applications; threshold voltage; CMOS technology; Ionization; Isolation technology; Low-frequency noise; Oxidation; Radiation hardening; Space technology; Testing; Threshold voltage; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Radiation and its Effects on Components and Systems, 1993.,RADECS 93., Second European Conference on

Conference_Location

St. Malo

Print_ISBN

0-7803-1793-9

Type

conf

DOI

10.1109/RADECS.1993.316574

Filename

316574