DocumentCode
2004563
Title
A detailed hardness evaluation of HCMOS devices
Author
David, J.P. ; Mondot, E. ; Villard, L.
Author_Institution
ONERA-CERT, Toulouse, France
fYear
1993
fDate
13-16 Sep 1993
Firstpage
344
Lastpage
348
Abstract
Experimental conditions have been established to achieve Radiation Verification Tests on non-hardened ICs. A realistic and conservative hardness evaluation of these devices has been carried out using a low dose rate irradiation and a 168 h/100°C annealing procedure. Most of the device types satisfied the conditions for a 20 krad application but a “super rebound” exceeding the maximum values ever seen appeared on one device type
Keywords
CMOS integrated circuits; annealing; integrated circuit testing; integrated logic circuits; radiation effects; 100 degC; 168 h; 20 krad; HCMOS devices; annealing procedure; logic family; low dose rate irradiation; radiation hardness evaluation; radiation verification tests; super rebound; Annealing; Current supplies; Degradation; Instruments; Interface states; Laboratories; MOS devices; Space technology; Testing; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Radiation and its Effects on Components and Systems, 1993.,RADECS 93., Second European Conference on
Conference_Location
St. Malo
Print_ISBN
0-7803-1793-9
Type
conf
DOI
10.1109/RADECS.1993.316576
Filename
316576
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