Impact of the source-path parasitic inductance on the MOSFET commutations

Today, the increase of the power densities requested by electronic applications have brought to a huge diffusion of high-performance power conversion systems that operate in switching-mode (e.g. switching mode power supply or SMPS). The realization of such converters demands for the use of power devices able to carry high density of currents, high blocking voltages, and high switching frequencies. In the meanwhile, since the volume reduction of the power converters asks for the size reduction of the electronic devices (smaller dimensions and increased performances), the impact of the parasitic phenomena starts to become more significant. In this paper, the parasitic effect of the internal source connection between the die and the package of MOSFETs has been analyzed. A demonstration board has been prepared to verify the impact of this parameter on both the commutation times and power losses. A comparison has been made between a conventional MOSFET and an innovative one that allows withdrawing the effect of the parasitic source inductance.