Fault models and test strategies for a two-bit per cell DRAM

This paper describes the development of a fault model and testing strategies for a 2-bit per cell dynamic random-access memory (DRAM). Multilevel DRAM technology may become an important way of increasing the storage density of semiconductor memory for a given process and minimum feature size. The Gillingham multilevel DRAM that we consider employs a multi-step sensing and restoring technique that re-uses many proven elements from a conventional 1-bit per cell DRAM cell array. Starting with a list of reported DRAM physical defects, we develop a logical fault model using both manual circuit analysis and analog circuit simulation. Several alternative testing strategies are proposed that make different trade-offs between testing cost and possible design for testability enhancements