Title :
A high-performance asynchronous FPGA: test results
Author :
Fang, David ; Teifel, John ; Manohar, Rajit
Author_Institution :
Comput. Syst. Lab., Cornell Univ., Ithaca, NY, USA
Abstract :
We report test results from a prototype asynchronous FPGA (AFPGA) implemented in TSMC´s 0.18 μm CMOS process. The AFPGA uses SRAM-based configuration bits with pipelined logic blocks and switch boxes. Test results demonstrate a throughput of 674 MHz at 1.8 V.
Keywords :
CMOS logic circuits; SRAM chips; asynchronous circuits; field programmable gate arrays; logic design; logic testing; CMOS process; SRAM-based configuration bits; TSMC; asynchronous FPGA; pipelined logic blocks; switch boxes; CMOS process; Clocks; Counting circuits; Field programmable gate arrays; Logic arrays; Routing; Switches; Testing; Throughput; Very large scale integration;
Conference_Titel :
Field-Programmable Custom Computing Machines, 2005. FCCM 2005. 13th Annual IEEE Symposium on
Print_ISBN :
0-7695-2445-1
DOI :
10.1109/FCCM.2005.9
