Performance and cost analysis of time-multiplexed execution on the dynamically reconfigurable processor

Author

Amano, Hideharu ; Abe, Shohei ; Hasegawa, Yohei ; Deguchi, Katsuaki ; Suzuki, Masayasu

Author_Institution

Dept. of Inf. & Comput. Sci., Keio Univ., Yokohama, Japan

fYear

2005

fDate

18-20 April 2005

Firstpage

315

Lastpage

316

Abstract

Dynamically reconfigurable processors with multi-context facility have been used for various applications. The relationship between context size and performance of such processors is analyzed based on real designs. The parallelism diagram which shows the required PEs in each step of the algorithm is introduced as the basis of the analysis, and models for performance and cost are shown. Evaluation results show that the performance is degraded about 23% when the size of a context becomes 1/2. The performance per cost is improved 7-14 times than that of the case without time-multiplexed execution.

Keywords

performance evaluation; reconfigurable architectures; system-on-chip; SoC; cost analysis; dynamically reconfigurable processor; parallelism diagram; performance analysis; time-multiplexed execution; Application software; Clocks; Computer science; Costs; Discrete cosine transforms; Hardware; Parallel processing; Performance analysis; Registers; Tiles;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines, 2005. FCCM 2005. 13th Annual IEEE Symposium on

Print_ISBN

0-7695-2445-1

Type

conf

DOI

10.1109/FCCM.2005.52

Filename

1508569