DocumentCode
2007318
Title
All-digital replica techniques for managing random mismatch in time-to-digital converters
Author
Sindia, Suraj ; Dai, Fa Foster ; Agrawal, Vishwani D.
Author_Institution
Dept. of Electr. & Comput. Eng., Auburn Univ., Auburn, AL, USA
fYear
2012
fDate
11-13 March 2012
Firstpage
130
Lastpage
134
Abstract
We propose replica techniques with statistical post processing to improve integral non-linearity (INL) and code distribution performance of time-to-digital converters (TDC). We consider three different types of TDC namely: vernier delay line, multi-resolution, and ring oscillator based. We show that using a replica delay line with additional digital processing at the output, one can achieve better INL and code distribution (at every code) in each of the TDC architectures. The quantum of improvement is only limited by the additional hardware that is to be added, and can be traded for arbitrarily high improvements in INL and code distribution.
Keywords
analogue-digital conversion; statistical analysis; TDC architectures; all-digital replica techniques; code distribution performance; digital processing; integral nonlinearity; replica delay line; ring oscillator; statistical post processing; time-to-digital converters; vernier delay line; CMOS integrated circuits; Calibration; Computer architecture; Delay; Delay lines; Hardware; Ring oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
System Theory (SSST), 2012 44th Southeastern Symposium on
Conference_Location
Jacksonville, FL
ISSN
0094-2898
Print_ISBN
978-1-4577-1492-4
Type
conf
DOI
10.1109/SSST.2012.6195156
Filename
6195156
Link To Document