A universal multistage interconnection network for large scale ATM switches

We propose a Universal Multistage Interconnection Network (UniMIN) for implementing large scale ATM switches which generally consist of an interconnection network and output switch modules. The proposed interconnection network, UniMIN is a modified delta network with output-buffered modules and it has modular expandability and self-routing capability. Any type output switch modules can be used with the proposed interconnection network, if they have good performance in terms of cell loss probability, delay, and throughput. The analytical and simulation study shows that the UniMIN switch architecture can yield high throughput; arbitrarily low cell loss probability, and reasonably low delay by simply adjusting the buffer size of interconnection module units. We expect that even a large scale 1024×1024 ATM switch can be implemented by utilizing the proposed architecture