DocumentCode
2007390
Title
An integrated Automatic Test Generation and executing system
Author
Huxun Chen ; Chen, Huxun ; Ye, Jinlin ; Cao, Weizhou ; Gao, Lei
Author_Institution
HeroTec Test & Control Ltd., Beijing, China
fYear
2011
fDate
12-15 Sept. 2011
Firstpage
383
Lastpage
390
Abstract
This paper presents an integrated Automatic Test Generation (ATG) and Automatic Test Executing/Equipment (ATE) system for complex boards. We developed an ATG technique called Behavior-Based Automatic Test Generation technique (namely BBATG). BBATG uses the device behavior fault model and represents a circuit board as interconnection of devices. A behavior of a device is a set of functions with timing relations on its in/out pins. When used for a digital circuit board test generation, BBATG utilizes device behavior libraries to drive behavior error signals and sensitize paths along one or multiple vectors so that a heavy and complicated iterating process can be avoided for sequential circuit test deductions. We have developed a complete set of test executing software and test supporting hardware for the ATE which can use the BBATG generated test data directly to detect behavior faults and diagnose faults at the device level for complex circuit boards. In addition, we have proposed and implemented useful technique, especially Design For Testability (DFT) [1][2] application technique on the integrated system, so the test generating/executing for complex boards with VLSI can be further simplified and optimized.
Keywords
automatic test equipment; automatic test pattern generation; design for testability; electronic engineering computing; fault simulation; interconnections; printed circuit testing; ATE; VLSI; automatic test executing/equipment system; behavior based automatic test generation technique; complex board; design for testability; device behavior fault model; device interconnection; digital circuit board test generation; drive behavior error signal; executing system; integrated automatic test generation; test executing software; test supporting hardware; Circuit faults; Integrated circuit modeling; Libraries; Pins; Printed circuits; Very large scale integration; Wires; Automatic Test Executing/Equipment (ATE); Automatic Test Generation (ATG); Behavior Fault Model; Design for Testability (DFT) application; Detect Test; Diagnosis Test; JTAG Device (Device with JTAG circuit);
fLanguage
English
Publisher
ieee
Conference_Titel
AUTOTESTCON, 2011 IEEE
Conference_Location
Baltimore, MD
ISSN
1088-7725
Print_ISBN
978-1-4244-9362-3
Type
conf
DOI
10.1109/AUTEST.2011.6058726
Filename
6058726
Link To Document