A novel technique for fast multiplication

Author

Sait, Sadiq M. ; Farooqui, Aamir A. ; Beckhoff, Gerhard F.

Author_Institution

King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia

fYear

1995

fDate

28-31 Mar 1995

Firstpage

109

Lastpage

114

Abstract

In this paper we present the design of a new high speed multiplication unit. The design is based on non-overlapped scanning of 3-bit fields of the multiplier. In this algorithm the partial products of the multiplicand and three bits of the multiplier are pre-calculated using only hardwired shifts. These partial products are then added using a tree of carry-save-adders, and finally the sum and carry vectors are added using a carry-look-ahead adder. In case of 2´s complement multiplication the tree of carry-save-adders also receives a correction output produced in parallel with the partial products. The algorithms is modeled in a hardware description language and its VLSI chip implemented. The performance of the new design is compared with other recent ones proposed in literature

Keywords

adders; digital arithmetic; multiplying circuits; 2´s complement multiplication; VLSI chip; carry vectors; carry-look-ahead adder; carry-save-adders; fast multiplication; hardware description language; hardwired shifts; multiplier; nonoverlapped scanning; partial products; Adders; Circuits; Costs; Delay effects; Digital signal processing chips; Hardware design languages; Minerals; Petroleum; Signal processing algorithms; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computers and Communications, 1995., Conference Proceedings of the 1995 IEEE Fourteenth Annual International Phoenix Conference on

Conference_Location

Scottsdale, AZ

Print_ISBN

0-7803-2492-7

Type

conf

DOI

10.1109/PCCC.1995.472503

Filename

472503