Fast parallel soft Viterbi decoder mapping on a reconfigurable DSP platform

The Viterbi algorithm is used to decode convolutional codes (CC). Viterbi decoding is a computation/communication intensive algorithm. Recently, with the emerging of WLAN standards delivering high rates, performance requirements of Viterbi decoders have increased dramatically. So far, such decoders have only been implemented using fixed ASIC with the datapath designed specially for the Viterbi algorithm, sacrificing flexibility. In this paper, we introduce a reconfigurable DSP platform targeting wireless communication algorithms in general with specific accelerators for the Viterbi algorithm.