• DocumentCode
    2008362
  • Title

    Clock tree tuning using shortest paths polygon

  • Author

    Saaied, Haydar ; Al-Khalili, Dhamin ; Al-Khalili, Asim J.

  • Author_Institution
    Concordia Univ., Montreal, Que., Canada
  • fYear
    2004
  • fDate
    12-15 Sept. 2004
  • Firstpage
    59
  • Lastpage
    62
  • Abstract
    A model to facilitate a better routing of a multiterminal net under obstacle constraints is presented. The model is applied to the clock tree routing problem. Using this model, in conjunction with simple routines, all possible locations of a Steiner node in the routing plane are determined. As a result, less wire length is achieved compared to other methods. The model has been incorporated in a local modification algorithm to efficiently implement engineering change orders (ECOs) of clock trees.
  • Keywords
    clocks; integrated circuit interconnections; integrated circuit modelling; network routing; Steiner node; clock tree tuning; engineering change orders; multiterminal net routing; obstacle constraints; shortest paths polygon; Bismuth; Clocks; Routing; Solids; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOC Conference, 2004. Proceedings. IEEE International
  • Print_ISBN
    0-7803-8445-8
  • Type

    conf

  • DOI
    10.1109/SOCC.2004.1362350
  • Filename
    1362350