A fully digitized multi-level demodulator for high-capacity digital radio systems

Proposes a new configuration for a fully digitized multi-level demodulator for application in high-capacity digital radio systems from the view points of small circuit scale and low sampling rate. The configuration is based on estimates of the performance of the digitized detector and timing filter by computer simulation. To implement the digitized detector, the authors build a Detector-LSI (DET-LSI) using 1.2-μm BiCMOS technology. The 16-QAM demodulator applied directly to STM-0 (51.84 Mbps) was constructed by using this LSI and a transversal equalizer as a timing filter. Experiments confirm that this demodulator improves system performance without precise adjustments