A flexible constraint length, foldable Viterbi decoder

The design and implementation of a novel reconfigurable Viterbi decoder which provides programmed flexibility between constraint length and decoder throughput is described. This flexibility is achieved through an architecture which employs a foldable state scheduling scheme allowing a wide range of constraint lengths to be processed by a fixed set of physical hardware at full utilization and with no change in system configuration. In addition, the design affords scalability allowing hardware growth for higher throughput. A rapid prototype implementation using FPGA technology is discussed. Results showing excellent performance of the decoder for a variety of constraint lengths, including K=14 which finds application in deep space communications, are presented