A standard cell automated layout for a CMOS 50 MHz 8*8 bit pipelined parallel Dadda multiplier

An 8*8 bit pipelined parallel multiplier which uses the Dadda scheme is presented. The multiplier has been implemented in a 3- mu m n-well CMOS process with two layers of metal using a standard cell automatic placement and routing program. The design uses a form of pipelined carry look-ahead adder in the final stage of summation, thus providing a significant contribution to the high performance of the multiplier. The design is expected to operate at a clock frequency of at least 50 MHz and has a flush time of seven clock cycles. The design illustrates a possible method of implementing an irregular architecture in VLSI using multiple levels of low-resistance, low-capacitance interconnect and automated layout techniques.<>