Performance evaluation of a source service node architecture under random traffic

Switching and multiplexing equipment constitute a significant portion of the overall ATM (asynchronous transfer mode) based broadband integrated services digital network (BISDN). Keeping their complexity low would ultimately lower the production and maintenance cost of the entire network. Although output buffers give the best switching performance, its implementation is costly. Switches that employ both input and output buffers attempt to compromise switching performance to lower the cost of output buffers. Although these switches display a significant improvement to those that employ only input buffer, their performance is never the less degraded by the inherent presence of head of line (HOL) blocking at their input ports. The impact of such blocking can be reduced at the source service node by also providing feedback and buffer at the concentrator stage prior to the switch fabric. In this paper, two such designs are proposed and evaluated: the available space and binary concentrator feedback architectures