Process and RF modelling of TSV last approach for 3D RF interposer

Author

Fuchs, C. ; Charbonnier, J. ; Cheramy, S. ; Cadix, L. ; Henry, D. ; Chausse, P. ; Hajji, O. ; Farcy, A. ; Garnier, G. ; Brunet-Manquat, C. ; Diaz, J. ; Anciant, R. ; Vincent, P. ; Sillon, N. ; Ancey, P.

Author_Institution

LETI, CEA, Grenoble, France

fYear

2011

fDate

8-12 May 2011

Firstpage

1

Lastpage

3

Abstract

In this paper, high density TSV integration in silicon interposer is presented, fully characterized and simulated (DC and RF). Parasitic elements of the RF model are extracted. Dielectric and metal process improvements are developed and their impact on TSV RF behaviour is evaluated. At least, silicon resistivity effect on TSV RF performances is demonstrated.

Keywords

dielectric materials; electrical resistivity; elemental semiconductors; integrated circuit modelling; radiofrequency integrated circuits; silicon; three-dimensional integrated circuits; 3D RF interposer; RF modelling; TSV RF behaviour; TSV RF performances; dielectric process improvement; high density TSV integration; metal process improvement; parasitic elements; resistivity effect; silicon interposer; Copper; Radio frequency; Silicon; Solid modeling; Substrates; Three dimensional displays; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference and 2011 Materials for Advanced Metallization (IITC/MAM), 2011 IEEE International

Conference_Location

Dresden

ISSN

pending

Print_ISBN

978-1-4577-0503-8

Type

conf

DOI

10.1109/IITC.2011.5940301

Filename

5940301