DocumentCode
2009872
Title
Low-power on-chip bus architecture using dynamic relative delays
Author
Ghoneima, Maged ; Ismail, Yehea
Author_Institution
Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
fYear
2004
fDate
12-15 Sept. 2004
Firstpage
233
Lastpage
236
Abstract
This paper proposes a dynamic delayed line bus scheme (DDL) for low-power on-chip buses. This scheme dynamically introduces a delay to bus lines having a certain switching activity to create relative delay between opposite switching adjacent lines. The optimum relative delay introduced by this proposed scheme is shown to reduce the power dissipation by up to 16%.
Keywords
delay lines; integrated circuit design; low-power electronics; system buses; bus lines; delay lines; dynamic delayed line bus scheme; dynamic relative delays; low-power on-chip bus architecture; optimum relative delay; power dissipation; switching adjacent lines; Capacitance; Clocks; Delay effects; Delay lines; Energy consumption; Energy dissipation; Power dissipation; Power system modeling; Switches; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2004. Proceedings. IEEE International
Print_ISBN
0-7803-8445-8
Type
conf
DOI
10.1109/SOCC.2004.1362419
Filename
1362419
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