Title :
Impact of through-silicon-via scaling on the wirelength distribution of current and future 3D ICs
Author :
Kim, Dae Hyun ; Lim, Sung Kyu
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
In this paper, we investigate the impact of TSV scaling on the wirelength distribution of the 3D ICs. This investigation includes wirelength distribution prediction of 3D ICs for current/future process/TSV technologies, studies on the impact of the design granularity at each process node, the impact of the die count, and the impact of TSV area constraint, and cross-comparison among various 2D and 3D technologies.
Keywords :
integrated circuit design; three-dimensional integrated circuits; 2D technology; 3D IC; 3D technology; TSV area constraint; TSV scaling; TSV technology; design granularity; die count; process node; process technology; through-silicon-via scaling; wirelength distribution prediction; Integrated circuit modeling; Logic gates; Predictive models; Solid modeling; Three dimensional displays; Through-silicon vias; Upper bound;
Conference_Titel :
Interconnect Technology Conference and 2011 Materials for Advanced Metallization (IITC/MAM), 2011 IEEE International
Conference_Location :
Dresden
Print_ISBN :
978-1-4577-0503-8
DOI :
10.1109/IITC.2011.5940324
