Title :
Address translation mechanisms in network interfaces
Author :
Schoinas, Ioannis ; Hill, Mark D.
Author_Institution :
Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
Abstract :
Good network hardware performance is often squandered by overheads for accessing the network interface (NI) within a host. NIs that support user-level messaging avoid frequent operating system (OS) action yet unnecessary copying can still result in low performance. We explore improving application messaging performance by eliminating all unnecessary copies (minimal messaging). For minimal messaging, NIs must support address translation and must do so more richly than has been done in the past. NI address translation should flexibly support higher-level abstractions, map all user space, exploit translation locality, and degrade gracefully, when locality is poor. We classify NI address translation implementations based on where the lookup and the miss handling are performed (CPU or NI). We present alternative designs and we consider how they interact with the OS. We provide simulation results that evaluate the alternative design points and we demonstrate feasibility with a real implementation using Myrinet. We find: NIs need not have hardware lookup structures, as software schemes are fast enough; it is difficult for an NI to handle its own translation misses unless commercial operating systems are substantially modified to view an NI as CPU peer; in the conventional situation where the operating system views the NI as a device, minimal messaging should be used only when the translation is present, while a single-copy protocol is used when it is not; and alternatively one can currently get acceptable performance when the CPU handle misses if the kernel provides very fast trap interfaces but microprocessor and operating system trends may make this alternative less viable in the long run
Keywords :
message passing; network interfaces; network operating systems; performance evaluation; protocols; CPU; Myrinet; address translation mechanisms; application messaging performance; copying; lookup; microprocessor; minimal messaging; miss handling; network hardware performance; network interfaces; operating system; simulation; single-copy protocol; translation locality; user-level messaging; Aerospace electronics; Birth disorders; Delay; Electronic switching systems; Government; Intelligent networks; Lab-on-a-chip; Network interfaces; Operating systems; Throughput;
Conference_Titel :
High-Performance Computer Architecture, 1998. Proceedings., 1998 Fourth International Symposium on
Conference_Location :
Las Vegas, NV
Print_ISBN :
0-8186-8323-6
DOI :
10.1109/HPCA.1998.650561