Title :
Scalability and Operating Voltage of Gate / N- Overlap LDD in Sub-half-micron Regime
Author :
Shimizu, M. ; Inuishi, M. ; Tsukamoto, K. ; Akasaka, Y.
Author_Institution :
LSI R&D Laboratory, Mitsubishi Electric Corporation, Japan
Keywords :
CMOS technology; Degradation; Hot carriers; Implants; Large scale integration; MOSFETs; Research and development; Scalability; Stress; Voltage;
Conference_Titel :
VLSI Technology, 1991. Digest of Technical Papers., 1991 Symposium on
Conference_Location :
Oiso, Japan
DOI :
10.1109/VLSIT.1991.705983
