Reliability testing and Failure Analysis of 3D integrated systems

3D integration comes with the introduction of many new processes and materials that may affect behavior and reliability of the overall system. For reliability testing of 3D integration technologies a 3-level test chip has been designed that includes Through Silicon Vias (TSV´s) and assembly layers and that allows evaluation of yield and electrical parameters under steady state (DC) and RF signal conditions. Additionally, this (stacked) chip delivers reliability values when used within the standardized procedures defined by JDEC. Subsequent Physical Failure Analysis has been performed using a novel plasma-FIB system that allows efficient chip access and first line analysis thanks to its high mill rates and good image resolution. In this paper, the test chip design, reliability testing and physical analysis details will be presented.