DocumentCode
2011417
Title
A pattern mining framework for inter-wafer abnormality analysis
Author
Sumikawa, N. ; Wang, L.-C. ; Abadir, M.S.
Author_Institution
Dept. of ECE, UC-Santa Barbara, Santa Barbara, CA, USA
fYear
2013
fDate
6-13 Sept. 2013
Firstpage
1
Lastpage
10
Abstract
This work presents three pattern mining methodologies for inter-wafer abnormality analysis. Given a large population of wafers, the first methodology identifies wafers with abnormal patterns based on a test or a group of tests. Given a wafer of interest, the second methodology searches for a test perspective that reveals the abnormality of the wafer. Given a particular pattern of interest, the third methodology implements a monitor to detect wafers containing similar patterns. This paper discusses key elements for implementing each of the methodologies and demonstrates their usefulness based on experiments applied to a high-quality SoC product line.
Keywords
flaw detection; integrated circuit testing; pattern recognition; semiconductor technology; system-on-chip; high-quality SoC product line; interwafer abnormality analysis; pattern mining framework; wafer pattern detection; Encoding; Image coding; Kernel; Pattern recognition; Semiconductor device modeling; Transforms; Vectors;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference (ITC), 2013 IEEE International
Conference_Location
Anaheim, CA
ISSN
1089-3539
Type
conf
DOI
10.1109/TEST.2013.6651890
Filename
6651890
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