A novel pipelined fast Fourier transform architecture for double rate OFDM systems

Author

Lin, Hsin-Lei ; Lin, Hongchin ; Chen, Yu-Chuan ; Chang, Robert C.

Author_Institution

Dept. of Electr. Eng., Nat. Chung-Hsing Univ., Taichung, Taiwan

fYear

2004

fDate

13-15 Oct. 2004

Firstpage

7

Lastpage

11

Abstract

A high throughput fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) processor for double-rate wireless LAN, based on double-rate OFDM communication systems, is proposed. It is an efficiently pipelined radix-2 FFT architecture, which doubles the throughput with significant hardware reduction. The utilization rate of multipliers and the processing elements reach 100%. The core size is 10 mm² with a power consumption of 208 mW at 20 MHz for data inputs with 15-bit word length, using 0.35 μm IP4M CMOS technology.

Keywords

CMOS logic circuits; OFDM modulation; digital signal processing chips; fast Fourier transforms; pipeline processing; wireless LAN; 0.35 micron; 15 bit; 20 MHz; 208 mW; CMOS; double rate OFDM systems; double-rate wireless LAN; high throughput FFT/IFFT processor; inverse fast Fourier transform; multiplier utilization rate; pipelined FFT architecture; processing elements; radix-2 FFT architecture; CMOS technology; Fast Fourier transforms; Hardware; MIMO; OFDM; Signal processing; Signal processing algorithms; Throughput; Wireless LAN; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 2004. SIPS 2004. IEEE Workshop on

Print_ISBN

0-7803-8504-7

Type

conf

DOI

10.1109/SIPS.2004.1363016

Filename

1363016