DocumentCode :
2011660
Title :
Process monitoring through wafer-level spatial variation decomposition
Author :
Ke Huang ; Kupp, Nathan ; Carulli, John M. ; Makris, Yiorgos
Author_Institution :
Dept. of Electr. Eng., Univ. of Texas at Dallas, Richardson, TX, USA
fYear :
2013
fDate :
6-13 Sept. 2013
Firstpage :
1
Lastpage :
10
Abstract :
Monitoring the semiconductor manufacturing process and understanding the various sources of variation and their repercussions is a crucial capability. Indeed, identifying the root-cause of device failures, enhancing yield of future production through improvement of the manufacturing environment, and providing feedback to the designer toward development of design techniques that minimize failure rate rely on such a capability. To this end, we introduce a spatial decomposition method for breaking down the variation of a wafer to its spatial constituents, based on a small number of measurements sampled across the wafer. We demonstrate that by leveraging domain-specific knowledge and by using as constituents dynamically learned, interpretable basis functions, the ability of the proposed method to accurately identify the sources of variation is drastically improved, as compared to existing approaches. We then illustrate the utility of the proposed spatial variation decomposition method in (i) identifying the main contributor to yield variation, (ii) predicting the actual yield of a wafer, and (iii) clustering wafers for production planning and abnormal wafer identification purposes. Results are reported on industrial data from high-volume manufacturing, confirming the ability of the proposed method to provide great insight regarding the sources of variation in the semiconductor manufacturing process.
Keywords :
integrated circuit design; integrated circuit manufacture; process monitoring; abnormal wafer identification; clustering wafers; design techniques; device failures; domain-specific knowledge; failure rate minimization; high-volume manufacturing; process monitoring; production planning; semiconductor manufacturing process; wafer-level spatial variation decomposition method; Clustering algorithms; Correlation; Manufacturing; Production; Semiconductor device measurement; Semiconductor device modeling; Systematics;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference (ITC), 2013 IEEE International
Conference_Location :
Anaheim, CA
ISSN :
1089-3539
Type :
conf
DOI :
10.1109/TEST.2013.6651901
Filename :
6651901
Link To Document :
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