HPC application in DSM/VDSM IC chip planning

By taking advantage of high performance computing technology, a dynamic parallel genetic algorithm (DPGA) has been developed in IHPC for DSM/VDSM chip planning. We present a new speckle model for searching optimal solutions in multi-dimensional space. Some new principles of peristalsis operators have been developed for density searching purposes. Dynamic control strategies in solution evaluation, ranking, crossover, mutation and peristalsis control have been developed. Parallel racial inheritance has implemented a two-dimension migration in the process. Compared with the sequential genetic algorithm with static control parameters (SSGA), some academic and industrial benchmark statistical results have shown that the average probability of reaching the optimal result within 3% error will be improved from 1%-10% to over 90% of cases. In chip planning, the DPGA 2.01 can speed up by 400 times compared with SSGA. The average design density could be improved bp 5-18% compared with SSGA. A patent was filed for DPGA on 23 June 1999.