• DocumentCode
    2011925
  • Title

    A reduced complexity decoder architecture via layered decoding of LDPC codes

  • Author

    Hocevar, Dale E.

  • Author_Institution
    DSP Solutions R&D Center, Texas Instruments, Dallas, TX, USA
  • fYear
    2004
  • fDate
    13-15 Oct. 2004
  • Firstpage
    107
  • Lastpage
    112
  • Abstract
    We apply layered belief propagation decoding to our previously devised irregular partitioned permutation LDPC codes. These codes have a construction that easily accommodates a layered decoding and we show that the decoding performance is improved by a factor of two in the number of iterations required. We show how our previous flexible decoding architecture can be adapted to facilitate layered decoding. This results in a significant reduction in the number of memory bits and memory instances required, in the range of 45-50%. The faster decoding speed means the decoder logic can also be reduced by nearly 50% to achieve the same throughput and error performance. In total, the overall decoder architecture can be reduced by nearly 50%.
  • Keywords
    computational complexity; iterative decoding; parity check codes; decoder logic; irregular LDPC codes; irregular partitioned permutation LDPC codes; iterations; layered belief propagation decoding; layered decoding; reduced complexity decoder architecture; Decoding; Parity check codes;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signal Processing Systems, 2004. SIPS 2004. IEEE Workshop on
  • Print_ISBN
    0-7803-8504-7
  • Type

    conf

  • DOI
    10.1109/SIPS.2004.1363033
  • Filename
    1363033