A low-power high-performance embedded SRAM macrocell

Author

Fahim, A.M. ; Khellah, M. ; Elmasry, M.I.

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

fYear

1998

fDate

19-21 Feb 1998

Firstpage

13

Lastpage

18

Abstract

A new approach to modeling the decoding hierarchy in a hierarchical word line (HWL) SRAM architecture using integer-linear programming (ILP) is introduced. Using this approach, the HWL architecture is shown to be inadequate for very large SRAM sizes. Alternatively, a new low-power high-speed SRAM architecture is described. This architecture is shown to have fairly constant speed and power dissipation for sizes ranging between 32 kb to 4 Mb. Low-power is achieved by a voltage boosting technique not requiring a two-step voltage and by a new method of tristating memory cells during a write operation. The SRAM was implemented in a 0.35 μm CMOS technology operated at 150 MHz while dissipating only 10 mW

Keywords

CMOS memory circuits; SRAM chips; cellular arrays; decoding; integer programming; linear programming; 0.35 micron; 10 mW; 150 MHz; 32 kbit to 4 Mbit; CMOS technology; decoding hierarchy; embedded SRAM macrocell; hierarchical word line; high-speed SRAM architecture; integer-linear programming; power dissipation; tristating; voltage boosting technique; write operation; Boosting; CMOS technology; Computer architecture; DSL; Decoding; Delay; Macrocell networks; Power dissipation; Random access memory; Semiconductor device modeling; Variable structure systems; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on

Conference_Location

Lafayette, LA

ISSN

1066-1395

Print_ISBN

0-8186-8409-7

Type

conf

DOI

10.1109/GLSV.1998.665192

Filename

665192