IDDQ testable design of static CMOS PLAs

Author

Hashizume, Masaki ; Hoshika, Hiroshi ; Yotsuyangi, H. ; Tamesada, Takeomi

Author_Institution

Fac. of Eng., Tokushima Univ., Japan

fYear

2000

fDate

2000

Firstpage

70

Lastpage

75

Abstract

A new IDDQ testable design method is proposed for static CMOS PLA circuits. A testable PLA circuit of the NOR-NOR type is designed by using this method. It is shown that all bridging faults in the NOR planes of the testable designed PLA circuit can be detected by IDDQ testing with 4 kinds of test input vectors. The test input vectors are independent of the logical functions to be realized in the PLA circuit. PLA circuits are designed by using this method so that the quiescent supply current generated when they are tested can be zero. Thus, a high resolution of IDDQ tests for the PLA circuits can be obtained by using this testable design method

Keywords

CMOS logic circuits; design for testability; integrated circuit design; integrated circuit testing; logic design; logic testing; programmable logic arrays; DFT; IDDQ testable design; NOR-NOR type; bridging faults; quiescent supply current; static CMOS PLAs; test input vectors; testable PLA circuits; Circuit faults; Circuit testing; Design methodology; Electrical fault detection; Fault detection; Field programmable gate arrays; Logic circuits; Logic functions; Logic testing; Programmable logic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect Based Testing, 2000. Proceedings. 2000 IEEE International Workshop on

Conference_Location

Montreal, Que.

Print_ISBN

0-7695-0637-2

Type

conf

DOI

10.1109/DBT.2000.843693

Filename

843693