• DocumentCode
    2012216
  • Title

    Improving the Test of NoC-Based SoCs with Help of Compression Schemes

  • Author

    Dalmasso, Julien ; Cota, Erika ; Flottes, Marie-Lise ; Rouzeyre, Bruno

  • Author_Institution
    LIRMM, Univ. de Montpellier/ CNRS, Montpellier
  • fYear
    2008
  • fDate
    7-9 April 2008
  • Firstpage
    139
  • Lastpage
    144
  • Abstract
    Re-using the network in a NoC-based system as a test access mechanism is an attractive solution as pointed out by several authors. As a consequence, testing of NoC-based SoCs is becoming a new challenge for designers. However, the effectiveness of testing methods is highly dependent on the number of test interfaces with the tester. This paper proposes the use of a test data compression scheme to increase the number of test interfaces (thus increasing test parallelism) without increasing the number of required automated test equipment (ATE) channels. We show that the combination of compression and NoC-based test scheduling allows a drastic reduction of the system test time at the expense of a very small area overhead.
  • Keywords
    circuit testing; data compression; network-on-chip; NoC-based SoC; compression schemes; test interfaces; test parallelism; testing methods; Automatic testing; Circuit testing; Computer Society; Costs; Job shop scheduling; Logic testing; Network-on-a-chip; Pins; System testing; Very large scale integration; Network on Chip; System on Chip Testing; Test Data Compression;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Symposium on VLSI, 2008. ISVLSI '08. IEEE Computer Society Annual
  • Conference_Location
    Montpellier
  • Print_ISBN
    978-0-7695-3291-2
  • Electronic_ISBN
    978-0-7695-3170-0
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2008.86
  • Filename
    4556784