A Programmable Frequency Divider in 0.18 um(micro-meter) CMOS Library

This paper presents a programmable frequency divider based on standard cell for digital video broadcasting-terrestrial (DVB-T) and other modern communication systems. As one of the components of PLL frequency synthesizer, this PFD cooperating with a dual-modulus prescaler can realize integer frequency division from 926 to 1381. The main steps of this divider design including logic synthesis, placement and routing are introduced. By back-annotating the back-end information to front-end design, the custom wire-load model is created for optimizing the design flow under deep submicron technology. This PFD has been fabricated using ARM TSMC 0.18 mum CMOS standard cell library with an area of 675 mumtimes475 mum and the power consumption is about 2 mW under 1.8 V power supply. Measurement results show that it is very successful in planned frequency division.