Title :
A 12-bit 2.5MS/s multi-channel ramp Analog-to-Digital Converter for Imaging detectors
Author :
Gao, Wu ; Hu-Guo, Christine ; Wei, Tingcun ; Gao, Deyuan ; Hu, Yann
Author_Institution :
Sch. of Comput. Sci. & Eng., Northwestern Polytech. Univ., Xi´´an
Abstract :
This paper presents a 12-bit multi-channel ramp Analog-to-Digital Converter (ADC) for Imaging detectors dedicated to high-energy physics and biomedical imaging applications. A two-level conversion scheme is employed to reduce the conversion time. The conventional Wilkinson-type architecture with a 5-bit Gray counter is used for coarse conversion while a multiphase sampling technique is proposed for fine conversion. An array of delay-locked loop is designed to generate 140-phase clocks so as to achieve a fine resolution of 7-bit. A one-channel prototype chip is designed in 0.35 mum CMOS technology. The maximum conversion time is measured as about 400 ns, which corresponds to a sample rate of about 2.5 MS/s. The power dissipation is about 3 mW/channel.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; delay lock loops; image resolution; image sampling; ramp generators; 5-bit Gray counter; CMOS technology; Wilkinson-type architecture; analog-to-digital converter; biomedical imaging application; delay-locked loop design; fine resolution; high-energy physics; imaging detector; multichannel ramp ADC; multiphase sampling technique; one-channel prototype chip design; phase clock; power dissipation; size 0.35 mum; two-level conversion scheme; Analog-digital conversion; Biomedical imaging; CMOS technology; Clocks; Counting circuits; Delay; Detectors; Physics; Prototypes; Sampling methods; Delay locked loop (DLL); Imaging detectors; analog-to-digital converter (ADC); ramp ADC;
Conference_Titel :
Imaging Systems and Techniques, 2009. IST '09. IEEE International Workshop on
Conference_Location :
Shenzhen
Print_ISBN :
978-1-4244-3482-4
Electronic_ISBN :
978-1-4244-3483-1
DOI :
10.1109/IST.2009.5071629
