• DocumentCode
    2012561
  • Title

    Integrated Power-Gating and State Assignment for Low Power FSM Synthesis

  • Author

    Pradhan, Sambhu Nath ; Kumar, M. Tilak ; Chattopadhyay, Santanu

  • Author_Institution
    Dept. of E & ECE, IIT, Kharagpur
  • fYear
    2008
  • fDate
    7-9 April 2008
  • Firstpage
    269
  • Lastpage
    274
  • Abstract
    Power-gating is an effective technique for reducing standby leakage power and dynamic power. In power-gating one can shut off the power supply to sections of logic block while keeping other logic blocks active. However, careful design is required to make power-gating technique effective, otherwise, negative effect of power-gating may overwhelm the potential gain. In this paper we have presented the state partitioning and state encoding strategy targeting low power finite state machine (FSM) decomposition based on genetic algorithmic approach. All the previous works dealt only FSM partitioning but did not consider state encoding together. This is the first ever approach considering FSM partitioning and state encoding together in power-gating technique. Experimental result shows that upto 73% power saving can be done giving small amount of area penalty.
  • Keywords
    VLSI; finite state machines; genetic algorithms; network synthesis; dynamic power; finite state machine decomposition; genetic algorithmic approach; logic block; low power FSM synthesis; power-gating; standby leakage power; state assignment; state encoding strategy; state partitioning; Automata; Batteries; Circuit synthesis; Costs; Encoding; Energy consumption; Genetics; Logic; Partitioning algorithms; Power supplies; FSM decomposition; Genetic Algorithm; Low power synthesis; Power-gating; State encoding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Symposium on VLSI, 2008. ISVLSI '08. IEEE Computer Society Annual
  • Conference_Location
    Montpellier
  • Print_ISBN
    978-0-7695-3291-2
  • Electronic_ISBN
    978-0-7695-3170-0
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2008.7
  • Filename
    4556806