Modeling and Optimization of Switching Power Dissipation in Static CMOS Circuits

This paper introduces a simple and yet accurate closed-form expression to estimate the switching power dissipation of static CMOS gates. The developed model depends on normalizing a gate- switching power to that of the unit standard inverter and it accounts for the effect of internodal capacitances. For different loads, gates and sizes, the developed model shows a good agreement with Spectre simulations using BSIM3v3 model and UMC 0.13 mum technology. The average error introduced by the model is about 2.7%. Moreover, the model has been used to optimize the switching power of a logical path under a specific required time constraint. For the considered scenarios, an average power saving of 20% and power-delay product of 23% are obtained compared to previous techniques.