DocumentCode
2012828
Title
Power reducing techniques for clocked CMOS PLAs
Author
Hobson, R.F.
Author_Institution
Sch. of Comput. & Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
fYear
1998
fDate
19-21 Feb 1998
Firstpage
34
Lastpage
38
Abstract
Power saving techniques for CMOS programmable logic arrays (PLAs) are discussed. Two new techniques are introduced, an AND-plane pulse generator, and wired-OR CMOS. Power reduction in excess of 75% over pseudo-NMOS techniques and 50% over some clocked PLA techniques is possible
Keywords
CMOS logic circuits; clocks; integrated circuit design; programmable logic arrays; pulse generators; AND-plane pulse generator; clocked CMOS PLAs; power reducing techniques; self-timed logic; single-phase clock; wired-OR CMOS; CMOS logic circuits; CMOS technology; Clocks; Delay; Energy consumption; Power engineering and energy; Power engineering computing; Programmable logic arrays; Pulse circuits; Pulse generation;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on
Conference_Location
Lafayette, LA
ISSN
1066-1395
Print_ISBN
0-8186-8409-7
Type
conf
DOI
10.1109/GLSV.1998.665196
Filename
665196
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