DocumentCode
20131
Title
Latency Analysis and Architecture Design of Simplified SC Polar Decoders
Author
Chuan Zhang ; Parhi, Keshab
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA
Volume
61
Issue
2
fYear
2014
fDate
Feb. 2014
Firstpage
115
Lastpage
119
Abstract
Recently, a low-latency decoding scheme called the simplified successive cancellation (SSC) algorithm has been proposed for polar codes. In this brief, we present the first systematic approach to formally derive the SSC decoding latency for any given polar code. The method to derive the SSC polar decoder architecture for any specific code is also presented. Moreover, the architecture of the precomputation SSC polar decoder is also proposed, which can further reduce the decoding latency. Compared with their SC decoder counterparts, the proposed SSC and precomputation SSC polar decoders can save up to 39.6% decoding latency with the same hardware cost.
Keywords
binary codes; decoding; tree codes; SSC decoding latency; architecture design; latency analysis; low-latency decoding; polar codes; precomputation; simplified SC polar decoders; simplified successive cancellation; specific code; Algorithm design and analysis; Clocks; Hardware; Maximum likelihood decoding; Schedules; Systematics; Binary tree; data-flow graph (DFG); polar codes; precomputation; simplified successive cancellation (SSC);
fLanguage
English
Journal_Title
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher
ieee
ISSN
1549-7747
Type
jour
DOI
10.1109/TCSII.2013.2291065
Filename
6680761
Link To Document