DocumentCode :
2013927
Title :
Test selection based on high level fault simulation for mixed-signal systems
Author :
Ozev, Sule ; Orailoglu, Alex
Author_Institution :
Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
fYear :
2000
fDate :
2000
Firstpage :
149
Lastpage :
154
Abstract :
Mixed-signal design and test tools are failing to keep pace with the increasing necessity for design exploration in the early stages. We outline a methodology and toolset to enable test selection at the early design stages by providing a high level fault simulator and associated block-level modeling and traversal capabilities. Experimental results show that the outlined methodology provides superior fault simulation speed-ups while helping to minimize the test time for a mixed-signal receiver system
Keywords :
automatic testing; circuit simulation; fault simulation; integrated circuit testing; mixed analogue-digital integrated circuits; block-level modeling; design exploration; high level fault simulation; mixed-signal systems; receiver system; simulation speed-ups; test selection; test time; traversal capabilities; Circuit faults; Circuit simulation; Circuit testing; Computational complexity; Computational modeling; Computer science; Computer simulation; Design engineering; Particle measurements; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2000. Proceedings. 18th IEEE
Conference_Location :
Montreal, Que.
ISSN :
1093-0167
Print_ISBN :
0-7695-0613-5
Type :
conf
DOI :
10.1109/VTEST.2000.843839
Filename :
843839
Link To Document :
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