Design of Low Logical Cost Conservative Reversible Adders Using Novel PCTG

Reversible Logic is one of the emerging computing technologies which assures zero power dissipation theoretically through thermodynamically proven principles. Its applications cover a wide spectrum starting with Low Power VLSI, quantum computing, Bio Informatics, Optical Circuits to Nanotechnology based systems. It can take in hand the issues of Fault tolerance through a special class of gates called parity conserving reversible logic gates. This paper aims to study the design a fault tolerant full adders using the new Parity Conserving Toffoli Gate, which is in turn employed to construct ripple carry adders, and high speed adders like carry skip adder. The design has the most optimized performance parameters in terms of Logical Cost than its counterparts in the literature.