Cold delay defect screening

Author

Tseng, Chao-Wen ; McCluskey, Edward J. ; Shao, Xiaoping ; Wu, David M.

Author_Institution

Center for Reliable Comput., Stanford Univ., CA, USA

fYear

2000

fDate

2000

Firstpage

183

Lastpage

188

Abstract

Delay defects can escape detection during the normal production test flow; particularly if they do not affect any of the long paths included in the test flow. Some delay defects can have their delay increased, making them easier to detect, by carrying out the test with a very low supply voltage (VLV testing). However, VLV testing is not effective for delay defects caused by high resistance interconnects. This paper presents a screening technique for such defects. This technique, cold testing, relies on carrying out the test at low temperature. One particular type of defect, silicide open, is analyzed and experimental data are presented to demonstrate the effectiveness of cold testing

Keywords

delays; integrated circuit interconnections; integrated circuit testing; low-temperature techniques; production testing; cold delay defects; defect screening; high resistance interconnects; production test flow; silicide open; Circuit faults; Circuit testing; Delay effects; Electrical capacitance tomography; Electrical fault detection; Fault detection; Integrated circuit interconnections; Silicides; Temperature; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 2000. Proceedings. 18th IEEE

Conference_Location

Montreal, Que.

ISSN

1093-0167

Print_ISBN

0-7695-0613-5

Type

conf

DOI

10.1109/VTEST.2000.843843

Filename

843843