Title :
Characterization of a pseudo-random testing technique for analog and mixed-signal built-in-self-test
Author :
Tofte, Jan Arild ; Ong, Chee Kian ; Huang, Jiun Lang ; Cheng, Kwang Ting
Author_Institution :
Mentor Graphics Corp., Wilsonville, OR, USA
Abstract :
In this paper, we characterize and evaluate the effectiveness of a pseudo-random-based implicit functional testing technique for analog and mixed-signal circuits. The analog test problem is transformed into the digital domain by embedding the device-under-test (DUT) between a digital-to-analog-converter and an analog-to-digital converter. The pseudo-random testing technique uses band-limited digital white noise (pseudo-random-patterns) as input stimulus. The signature is constructed by computing the cross-correlation between the digitized output response and the pseudo-random input sequence. We have implemented a DSP-based hardware testbed to evaluate the effectiveness of the pseudo-random testing technique. Our results show that we can achieve close to 100% yield and fault coverages by carefully selecting only two cross-correlation samples. Noise level and total harmonic distortion below 0.1% and 0.5%, respectively, do not affect the classification accuracy
Keywords :
analogue-digital conversion; application specific integrated circuits; built-in self test; digital-analogue conversion; fault diagnosis; harmonic distortion; integrated circuit testing; mixed analogue-digital integrated circuits; white noise; DSP-based hardware testbed; analog-to-digital converter; band-limited digital white noise; cross-correlation; cross-correlation samples; device-under-test; digital-to-analog-converter; digitized output response; fault coverage; implicit functional testing technique; input stimulus; mixed-signal built-in-self-test; pseudo-random input sequence; pseudo-random testing technique; total harmonic distortion; Analog-digital conversion; Application specific integrated circuits; Built-in self-test; Circuit testing; Costs; Delay; Hardware; Logic testing; Phase locked loops; Signal generators;
Conference_Titel :
VLSI Test Symposium, 2000. Proceedings. 18th IEEE
Conference_Location :
Montreal, Que.
Print_ISBN :
0-7695-0613-5
DOI :
10.1109/VTEST.2000.843851