Title :
DEFUSE: a deterministic functional self-test methodology for processors
Author :
Chen, Li ; Dey, Sujit
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
Abstract :
At-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-test. However, due to their reliance on random patterns, current logic BIST techniques are not able to deal with large designs without adding high test overhead. In this paper, we propose a functional self-test technique that is deterministic in nature. By targeting the structural test need of manageable components with the aid of processor functionality, this technique has the fault coverage advantage of deterministic structural testing and the at-speed advantage of functional testing. Most importantly, by relieving testers from test application, it enables at-speed testing of GHz processors with low speed testers. We have demonstrated our methodology on a simple accumulator-based microprocessor. The results show that with the proposed technique, we are able to apply high-quality at-speed tests with no test overhead
Keywords :
built-in self test; divide and conquer methods; integrated circuit testing; logic testing; microprocessor chips; BIST; accumulator-based microprocessor; at-speed testing; deterministic functional self-test methodology; deterministic structural testing; functional self-test technique; functional testing; processor functionality; test overhead; Automatic testing; Built-in self-test; Electronics industry; Logic design; Logic testing; Manufacturing; Microprocessors; Semiconductor device testing; Test equipment; Test pattern generators;
Conference_Titel :
VLSI Test Symposium, 2000. Proceedings. 18th IEEE
Conference_Location :
Montreal, Que.
Print_ISBN :
0-7695-0613-5
DOI :
10.1109/VTEST.2000.843853