DocumentCode :
2014327
Title :
Using arithmetic transform for verification of datapath circuits via error modeling
Author :
Radecka, Katarzyna ; Zilic, Zeljko
Author_Institution :
Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, Que., Canada
fYear :
2000
fDate :
2000
Firstpage :
271
Lastpage :
277
Abstract :
In this paper, we consider verification under error-model assumption. We exploit the algebraic properties of the arithmetic transforms that are used in compact graph-based representations of arithmetic circuits, such as *BMDs. Verification time can be shortened under the assumption of corrupting a bounded number of transform coefficients. Bounds are derived for a number of test vectors, and the vectors successfully verified arithmetic circuits under a class of error models derived from recently proposed basic design error classes, including single stuck-at faults
Keywords :
application specific integrated circuits; decision diagrams; fault diagnosis; graph theory; integrated circuit testing; logic testing; transforms; *BMDs; algebraic properties; arithmetic circuits; arithmetic transform; compact graph-based representations; datapath circuits; error modeling; single stuck-at faults; test vectors; transform coefficients; verification time; Arithmetic; Boolean functions; Circuit faults; Computer errors; Data structures; Delay; Libraries; Microprocessors; Polynomials; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2000. Proceedings. 18th IEEE
Conference_Location :
Montreal, Que.
ISSN :
1093-0167
Print_ISBN :
0-7695-0613-5
Type :
conf
DOI :
10.1109/VTEST.2000.843855
Filename :
843855
Link To Document :
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