New high-speed CMOS full adder cell of mirror design style

A new circuit of a high-speed CMOS full adder cell is presented. The proposed adder cell refers to the CMOS adders class executed on CMOS mirror design style, with the attributes intrinsic to this class: absence of power consumption in a static mode, absence of incomplete levels of voltages inside the circuit and, hence, necessity to restore these levels. The proposed solution of adder cell provides a higher speed of carry signal formation as compared to the known adders and, hence, allows achieving high speed of the N-bit adder device. The proposed cell has been compared to the other three basic cells.